When people talk about AI chip capacity, the first thing they think of is “3nm process nodes.” Three nanometers, two nanometers—it feels like process is the core bottleneck. But over the past two years, what has really constrained NVIDIA’s shipments has not been the process node, but advanced packaging. More specifically, TSMC’s CoWoS.
Today, whether one NVIDIA Blackwell or one AMD MI300 can be delivered on time depends almost entirely on how many CoWoS wafers TSMC can open up that month.
First, let me explain what CoWoS is.
Its full name is Chip on Wafer on Substrate, literally “chip on wafer then attached to substrate.”
A traditional chip is a single die packaged onto a substrate. CoWoS takes multiple dies—a GPU core plus several HBM stacks—attaches them first onto a silicon interposer, uses the silicon interposer for high-density, short-distance interconnects, and then attaches the whole assembly onto the substrate.
Why is this necessary?
Because what the GPU core and HBM need is bandwidth of several TB per second, and ordinary PCB routing simply cannot handle that density. Only the micron-scale wiring in a silicon interposer can do it.
So CoWoS is the process that “stitches” the GPU and HBM together. Without it, HBM cannot be placed next to the GPU, and the “memory wall” from the previous episode cannot be bypassed.
The difficulty with CoWoS is that it has two main forms:
CoWoS-S uses a silicon interposer; the process is mature, but the interposer cannot be made very large;
CoWoS-L uses RDL plus local silicon bridges, and can create an extra-large package, supporting NVIDIA’s Blackwell monster, which stitches together two compute dies and eight HBM stacks.
NVIDIA’s CEO made it clear in early 2025 that Blackwell is being fully transitioned from CoWoS-S to CoWoS-L. This switch means the entire packaging line has to be rebuilt, and capacity ramp-up starts from zero.
The capacity numbers are tighter than people imagine.
TSMC’s monthly CoWoS capacity was about 35,000 wafers at the end of 2024, is set to double to 75,000 wafers by the end of 2025, and is targeted to reach 125,000 to 130,000 wafers by the end of 2026.
That looks like a doubling each year, but demand is growing even faster. TrendForce estimates that even at this expansion pace, the CoWoS supply-demand gap will only narrow from 20% at the start of 2026 to around 10% by the end of the year.
In other words, throughout 2026, how many GPUs NVIDIA can sell is not decided by NVIDIA itself, but by TSMC’s CoWoS workshop.
Why is expansion so slow? Three reasons.
First, CoWoS uses specialized bonding, placement, and testing equipment, not ordinary fab equipment, and there are only a few suppliers. Scaling that capacity takes time by nature.
Second, CoWoS-L is more complex than CoWoS-S. Yield ramp-up takes time, and a new factory being completed does not mean it can run at full capacity.
Third, CoWoS needs coordination with the upstream and downstream parts of the HBM chain. HBM stacking yield is also ramping up, and if any link is blocked, the whole line gets stuck.
So the role of advanced packaging in the AI supply chain is very clear today: it is a bottleneck that is harder, slower, and more concentrated than the process node.
At present, TSMC is the only company in the world capable of mass-producing CoWoS-L, while Samsung and Intel Foundry are still catching up.
This layer may seem unremarkable, but in TSMC’s quarterly calls, the two numbers that matter most for judging real GPU supply are “HPC mix” and “advanced packaging capacity.” They are the most sensitive thermometer.