When talking about Nvidia’s rivals, there’s not only AMD, but also a group of players that are more hidden and even more worth paying attention to — the AI chips made by hyperscalers themselves. Google’s TPU, Amazon’s Trainium, Meta’s MTIA, Microsoft’s Maia. They are not directly competing with Nvidia in the same market, but they are all quietly eating into Nvidia’s share.
First, look at the scale.
Industry estimates put the combined deployment of hyperscaler in-house chips at about 1.9 million accelerators in 2026, a considerable proportion of Nvidia’s shipments. TPU v6 (Trillium) and MTIA v3 are already running formally in Google’s and Meta’s production environments, and AWS Trainium3 has also reached 3nm and 144GB HBM3E per card. In terms of hardware specs, this batch of chips is already at the same level as Nvidia.
The logic of in-house ASICs is very simple:
When hyperscalers buy Nvidia GPUs, they have to pay a 75% gross margin premium. If they make a chip themselves that only serves their own workloads, costs can be cut by more than half. Even after factoring in one-time design expenses, software stack development, and engineering teams, the unit compute cost still comes down after large-scale deployment. So every hyperscaler has a strong incentive to do this.
But ASICs also have very clear ceilings, and this is the key to understanding this main line of development.
First, ASICs are for “self-use.”
They only run their own frameworks and their own workloads, and are not sold externally. TPU is only used internally by Google Cloud, and Trainium is only used internally by AWS. That means they cannot form a general-purpose market, nor can they spread development costs across customers and scenarios the way Nvidia can.
Second, ASICs require their own software stack.
TPU uses XLA and JAX, while Trainium has the Neuron SDK. These software stacks only mature within the hyperscaler’s own closed loop. Hyperscaler engineers can use them, but external AI companies almost never touch them. This limits the practical scope of ASIC usage.
Third, ASIC iteration is slower than GPU iteration.
Nvidia rolls out a new architecture every year, while hyperscaler in-house chips generally come in one generation every two to three years. That’s because designing a new chip, mass-producing it, deploying it, and tuning it all take time. When Nvidia doubles performance with each generation, ASICs can easily be left behind.
Fourth, frontier training still can’t avoid Nvidia.
When hyperscalers train top-tier models themselves, most core training tasks still remain on Nvidia clusters. TPU and MTIA are used more for inference, as well as some relatively well-defined training tasks. That’s because frontier training is extremely experimental and requires the rich debugging and optimization tools in the CUDA ecosystem; the in-house ASIC ecosystem has not reached that stage yet.
So for Nvidia, ASICs mean “steady bleeding,” not “disruptive replacement.” They will keep nibbling away at Nvidia’s share in inference, and in hyperscaler self-use training, perhaps pushing Nvidia’s market share from 80% down to 60% or even lower over the long run. But in the short term, they will not knock Nvidia off its pedestal, because the universality of the CUDA ecosystem, the pace of iteration, and the scale of the external market are all things hyperscaler in-house chips cannot cover.
For investors, the implication is: ASICs are a long-term valuation discount factor for Nvidia, not a short-term collapse factor.
Looking at this thread, the signal to watch is the deployment ratio of in-house ASICs inside the hyperscalers — if Google’s internal TPU share rises from about half today to 80%, or if AWS Trainium’s inference share goes above half, that would be the real inflection point.
Before that, Nvidia is still the center of pricing power in this market.